The minimum time for which the input
signal has to be maintained at the
input of flip - flop is called ______ of
the flip - flop .
Set - up time
Hold time 242
Pulse Interval time
Pulse Stability time (PST)
The glitches due to " Race Condition"
can be avoided by using a ___________
Gated flip - flops
Pulse triggered flip - flops
Positive - Edge triggered flip - flops
Negative- Edge triggered flip - flops
267
We have a digital circuit . Different
parts of circuit operate at different
clock frequencies ( 4 MHZ , 2 MHZ and
1 MHZ ), but we have a single clock
source having a fix clock frequency
(4 MHZ ) , to supply the required
frequency to each part of circuit , we
can get help by using ___________
Using
S- R Flop- Flop
D - flipflop
J - K flip - flop
T- Flip - Flop
Once the state diagram is drawn for
any sequential circuit the next step is
to draw
Transiation table
Karnaugh map
Next- state table 306
Logic expression
A synchronous decade counter will have
_______ flip - flops
3 ,
7 ,
4 ,
10
For a gated D - Latch if EN= 1 and D = 1
then Q ( t + 1 ) =
0 ,
1 ,
Q( t )
valid
If a circuit suffers “ Clock Skew “
problem, the output of circuit can ’ t be
guarantied .
True
false
The 74 HC 163 is a 4 - bit Synchronous
Counter .it has . .... ... ... ...parallel data
inputs pins
2
,4
,6
,8
The _____________ input overrides the
________ input
Asynchronous, synchronous 235
Synchronous, asynchronous
Preset input (PRE ) , Clear input ( CLR )
Clear input ( CLR ), Preset input ( PRE )
A standard interface for programming
the In - System PLD consists of
2 wire ,
4 wire 194
8 wire ,
16 wire
