Question # 1 of 10 ( Start time: 08:14:13 PM ) Total Marks: 1
A positive edge-triggered flip-flop changes its state when ________________
Select correct option:
Enable input (EN) is set
Preset input (PRE) is set
Low-to-high transition of clock ok
High-to-low transition of clock
Question # 2 of 10 ( Start time: 08:14:38 PM ) Total Marks: 1
In a 4-bit binary counter, the next state after the terminal count in the DOWN mode is ____________
Select correct option:
0000 ok
1111
0001
10000
Question # 3 of 10 ( Start time: 08:15:00 PM ) Total Marks: 1
In asynchronous digital systems all the circuits change their state with respect to a common clock
Select correct option:
True
False ok
Question # 4 of 10 ( Start time: 08:15:35 PM ) Total Marks: 1
Divide-by-32 counter can be acheived by using
Select correct option:
Flip-Flop and DIV 10
Flip-Flop and DIV 16 not confirm
Flip-Flop and DIV 32
DIV 16 and DIV 32
Question # 5 of 10 ( Start time: 08:16:37 PM ) Total Marks: 1
The Synchronous counters are also known as Ripple Counters:
Select correct option:
True
False ok
Question # 6 of 10 ( Start time: 08:17:34 PM ) Total Marks: 1
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is
Select correct option:
10 mW
25 mW ok
64 mW
1024 mW
Question # 7 of 10 ( Start time: 08:18:44 PM ) Total Marks: 1
Asynchronous mean that_____________
Select correct option:
Each flip-flop after the first one is enabled by the output of the preceding flip-flop
Each flip-flop is enabled by the output of the preceding flip-flop
Each flip-flop except the last one is enabled by the output of the preceding flip-flop
Each alternative flip-flop after the first one is enabled by the output of the preceding flip-flop
Question # 8 of 10 ( Start time: 08:20:11 PM ) Total Marks: 1
A counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status.
Select correct option:
3
7
8 ok
15
Question # 9 of 10 ( Start time: 08:20:56 PM ) Total Marks: 1
A mono -stable device only has a single stable state
Select correct option:
True ok
False
Question # 10 of 10 ( Start time: 08 :21:37 PM ) Total Marks: 1
When the both inputs of edge-triggered J-K flop-flop are set to logic zero _________
Select correct option:
The flop-flop is triggered
Q=0 and Q’=1
Q=1 and Q’=0 ok
The output of flip-flop remains unchanged
