Question # 1 of 10 ( Start time: 07:19:44 PM ) Total Marks: 1
A negative edge-triggered flip-flop changes its state when________________
Select correct option:
Enable input (EN) is set
Preset input (PRE) isset
Low- to-high transition of clock
High-to-low transition of clock ok
Question # 2 of 10 ( Start time: 07:20:42 PM ) Total Marks: 1
Flip flops are also called _____________
Select correct option:
Bi- stable multivibrators ok
Bi- stable singlevibrators
Bi- stable dualvibrators
Bi- stable transformer
Question # 3 of 10 ( Start time: 07:21:05 PM ) Total Marks: 1
___________is oneof the examples of asynchronous inputs.
Select correct option:
J-K input ok
S-R input
D input
Clear Input (CLR)
Question # 4 of 10 ( Start time: 07:21:21 PM ) Total Marks: 1
The terminal count of a 4-bit binary counter in the DOWN mode is ____________
Select correct option:
0000 ok
0011
1100
1111
Question # 5 of 10 ( Start time: 07:21:44 PM ) Total Marks: 1
The terminal count of a 4-bit binary counter in the UP mode is ____________
Select correct option:
1100
0011
1111 ok (notconfirm)
0000
Question # 6 of 10 ( Start time: 07:23:15 PM ) Total Marks: 1
Each stage of Master-slaveflip- flop works at ____ of the clocksignal
Select correct option:
Each stage works on complete clocksignal
One fourth
One third
One half ok
Question # 7 of 10 ( Start time: 07:23:35 PM ) Total Marks: 1
____________is said to occur when multiple internal variables change due to change in oneinput variable
Select correct option:
Hold and Wait
Clock Skew
Race condition ok
Hold delay
Question # 8 of 10 ( Start time: 07:24:04 PM ) Total Marks: 1
Three cascaded modulus-10 counters have an overall modulus of
Select correct option:
30
100
1000
10000 ok
Question # 9 of 10 ( Start time: 07:25:36 PM ) Total Marks: 1
If a circuit suffers “Clock Skew “ problem, the output of circuit can ’ t be guarantied.
Select correct option:
True
False ok
