CS302 Final term Paper Solved 2010 - 3

FINALTERM  EXAMINATION

Spring 2010

CS302- Digital Logic Design 

Time: 90 min

M a r k s: 58

    

Question No: 1    ( M a r k s: 1 )    http://vuzs.net

  

A 8-bit serial in / parallel out shift register contains the value “8”, _____ clock signal(s) will be required to shift the value completely out of the register.

       ► 1

       ► 2

       ► 4

       ► 8

   

Question No: 2    ( M a r k s: 1 )    http://vuzs.net

  

A frequency counter ______________

       ► Counts pulse width

       ► Counts no. of clock pulses in 1 second

       ► Counts high and low range of given clock pulse

       ► None of given options

Question No: 3    ( M a r k s: 1 )    http://vuzs.net

 

In a sequential circuit the next state is determined by ________ and _______

       ► State variable, current state

       ► Current state, flip-flop output

       ► Current state and external input

       ► Input and clock signal applied

Question No: 4    ( M a r k s: 1 )    http://vuzs.net

 

 The divide-by-60 counter in digital clock is implemented by using two cascading counters:

       ► Mod-6, Mod-10

       ► Mod-50, Mod-10

       ► Mod-10, Mod-50

       ► Mod-50, Mod-6

   

Question No: 5    ( M a r k s: 1 )    http://vuzs.net

 

 In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained.

       ► True

       ► False

   

Question No: 6    ( M a r k s: 1 )    http://vuzs.net

  

Flip flops are also called _____________

       ► Bi-stable dualvibrators

       ► Bi-stable transformer

       ► Bi-stable multivibrators

       ► Bi-stable singlevibrators

   

Question No: 7    ( M a r k s: 1 )    http://vuzs.net

  

The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.

       ► Set-up time

       ► Hold time

       ► Pulse Interval time

       ► Pulse Stability time (PST)

   

Question No: 8    ( M a r k s: 1 )    http://vuzs.net

 

74HC163 has two enable input pins which are _______ and _________

       ► ENP, ENT

       ► ENI, ENC

       ► ENP, ENC

       ► ENT, ENI

   

Question No: 9    ( M a r k s: 1 )    http://vuzs.net

 ____________ is said to occur when multiple internal variables change due to change in one input variable

       ► Clock Skew

       ► Race condition

       ► Hold delay

       ► Hold and Wait

   

Question No: 10    ( M a r k s: 1 )    http://vuzs.net

  

Given the state diagram of an up/down counter, we can find __________

       ► The next state of a given present state

       ► The previous state of a given present state

       ► Both the next and previous states of a given state

       ► The state diagram shows only the inputs/outputs of a given states

    

 Question No: 11    ( M a r k s: 1 )    http://vuzs.net

  

The _____________ input overrides the ________ input

       ► Asynchronous, synchronous

       ► Synchronous, asynchronous

       ► Preset input (PRE), Clear input (CLR)

       ► Clear input (CLR), Preset input (PRE)

   

Question No: 12    ( M a r k s: 1 )    http://vuzs.net

  

A logic circuit with an output  consists of ________.

       ► two AND gates, two OR gates, two inverters

       ► three AND gates, two OR gates, one inverter

       ► two AND gates, one OR gate, two inverters

       ► two AND gates, one OR gate

   

Question No: 13    ( M a r k s: 1 )    http://vuzs.net

A decade counter is __________.

       ► Mod-3 counter

       ► Mod-5 counter

       ► Mod-8 counter

       ► Mod-10 counter

Question No: 14    ( M a r k s: 1 )    http://vuzs.net

  

In asynchronous transmission when the transmission line is idle, _________

       ► It is set to logic low

       ► It is set to logic high

       ► Remains in previous state

       ► State of transmission line is not used to start transmission

   

Question No: 15    ( M a r k s: 1 )    http://vuzs.net

  

A Nibble consists of _____ bits

       ► 2

       ► 4

       ► 8

       ► 16

   

Question No: 16    ( M a r k s: 1 )    http://vuzs.net

  

The output of this circuit is always ________.

       ► 1

       ► 0

       ► A

       ►

   

Question No: 17    ( M a r k s: 1 )    http://vuzs.net

 

 Excess-8 code assigns _______ to “-8”

       ► 1110

       ► 1100

       ► 1000

       ► 0000

   

Question No: 18    ( M a r k s: 1 )    http://vuzs.net

 

The voltage gain of the Inverting Amplifier is given by the relation ________

       ► V_out / V_in = - R_f / R_i

       ► V_out / R_f = - V_in / R_i

       ► R_f / V_in = - R_i / V_out

       ► R_f / V_in =   R_i / V_out

   

Question No: 19    ( M a r k s: 1 )    http://vuzs.net

  

LUT is acronym for _________

       ► Look Up Table

       ► Local User Terminal

       ► Least Upper Time Period

       ► None of given options

   

Question No: 20    ( M a r k s: 1 )    http://vuzs.net

  

DRAM stands for __________

       ► Dynamic RAM

       ► Data RAM

       ► Demoduler RAM

       ► None of given options

   

Question No: 21    ( M a r k s: 1 )    http://vuzs.net

  

The three fundamental gates are ___________

       ► AND, NAND, XOR

       ► OR, AND, NAND

       ► NOT, NOR, XOR

       ► NOT, OR, AND

   

   

Question No: 22    ( M a r k s: 1 )    http://vuzs.net

 

Which of the following statement is true regarding above block diagram ?

       ► Triggering takes place on the negative-going edge of the CLK pulse

       ► Triggering takes place on the positive-going edge of the CLK pulse

       ► Triggering can take place anytime during the HIGH level of the CLK waveform

       ► Triggering can take place anytime during the LOW level of the CLK waveform

   

Question No: 23    ( M a r k s: 1 )    http://vuzs.net

 

   

The total amount of memory that is supported by any digital system depends upon ______

       ► The organization of memory

       ► The structure of memory

       ► The size of decoding unit

       ► The size of the address bus of the microprocessor

Question No: 24    ( M a r k s: 1 )    http://vuzs.net

  

The expression F=A+B+C describes the operation of three bits _____ Gate.

       ► OR

       ► AND

       ► NOT

       ► NAND

   

Question No: 25    ( M a r k s: 1 )    http://vuzs.net

  

Stack is an acronym for _________

       ► FIFO memory

       ► LIFO memory

       ► Flash Memory

       ► Bust Flash Memory

   

Question No: 26    ( M a r k s: 1 )    http://vuzs.net

  

Addition of two octal numbers “36” and “71” results in ________

       ► 213

       ► 123

       ► 127

       ► 345

   

Question No: 27    ( M a r k s: 2 )

  

Define quantization process.

    

Question No: 28    ( M a r k s: 2 )

Explain the difference between 1-to-4 Demultiplexer and 2-to-4 Binary Decoder? 

Question No: 29    ( M a r k s: 2 )

 

A general Sequential circuit consists of a combinational circuit and a memory element. How this memory element is implemented

Question No: 30    ( M a r k s: 2 )

 

Suppose a 2 bit up-counter, having states “A, B, C, D”. Write down GOTO statements to show how present states change to next states.

Question No: 31    ( M a r k s: 3 )

  

Name three Operations that can be performed on FLASH Memory

   

Question No: 32    ( M a r k s: 3 )

  

Explain Rotate Right Operation of shift register with the help of diagram.

    

Question No: 33    ( M a r k s: 3 )

 

You are given the block diagram of 74HC190 integrated circuit up/down counter, explain the function of labeled inputs/outputs.

Question No: 34    ( M a r k s: 5 )

 

 Draw the state diagram of 3-bit up-down counter, use an external input X, when X sets to logic 1, the counter counts downwards, otherwise upward.

   

Question No: 35    ( M a r k s: 5 )

 Differentiate between synchronous and asynchronous RAM.

Question No: 36    ( M a r k s: 5 )

Explain Memory Select or Enable Signals